logisim-evolved

Why rebuild it

logisim-evolution is the circuit simulator a lot of first computer-organisation courses run on, including CSC258 at the University of Toronto, whose coursework is the test corpus here. On a Mac it shows its age in ways a student notices in the first week. Every launch asks for permission to accept incoming network connections, because the app opens a listening port for a VHDL co-simulation bridge almost nobody uses. The build fails Gatekeeper. The canvas is capped at 20 frames a second, and you cannot place anything left of the leftmost component. Re-saving a file that uses an unknown library silently drops those components.

The one I cared about most is the clock. Upstream schedules each tick from the moment it noticed the previous one, so the time spent propagating signals is added to every period and the error accumulates. A circuit set to 1 Hz is not running at 1 Hz, and the frequency readout shows what you asked for, not what you got.

How it works

The simulation kernel is a synchronous, single-threaded propagation loop, kept deliberately close to the original so behaviour can be compared rule for rule. The clock schedules every tick from a fixed origin, tick n due at t0 + n × period, and waits on a real-time (THREAD_TIME_CONSTRAINT_POLICY) thread instead of spinning a core near each deadline. Simulation time is decoupled from drawing.

Components draw into a retained scene that is culled to the viewport and rendered with Core Graphics, which is what removes the frame cap. Files round-trip byte for byte, including 4.1.0's quirks, and anything from a library this version does not know is kept as an opaque placeholder rather than deleted. Generated VHDL and Verilog match the original exactly, down to signal names that depend on the iteration order of a Java hash set, which the port reproduces on purpose.

Checked against the original

The bar is not “it runs” but “it produces the same bytes”. Bridges drive the real 4.1.0 release and compare output: edit sequences replayed in both and the saved files diffed, HDL generated from the same circuits, and simulation traces from a corpus of real course work. Where a test can see an upstream bug, the port keeps it, because a student's saved circuit depends on it; where it cannot, it is fixed. 4.1.0's Minimize buttons, for one, do nothing on any circuit built from a truth table, and here they work.

In a side-by-side run of the two scheduling rules, the fixed-origin clock held:

Clock rate	Drift, upstream rule	Drift, fixed origin
1 Hz	80.3 ms	3.6 µs
100 Hz	8.71 ms	1.2 µs
10 kHz	7.22 ms	251 µs

At 10 kHz the upstream rule saturates a core, 99.6%, spinning near each deadline; the fixed origin does the same work at 22.8%. The suite is 1,757 tests, plus 15 recorded edit sequences that come out byte-identical to the original.

Where it stands

It started on 4 September 2026 and went public ten days later as a pre-release, 0.1.0. Full parity with 4.1.0 is what 1.0 means, and it is not there yet: the finite-state-machine editor is missing, the hex editor exists but cannot be reached, and some labels still misbehave in dark mode. It runs on macOS 26, Apple silicon first, and ships as a signed, notarised download from GitHub Releases.

It is GPL-3.0, like the project it comes from, which is also why it will not be on the App Store: Apple's terms and the GPL do not mix. The circuits, the components and the idea are Carl Burch's original Logisim and the logisim-evolution contributors'; this is a new body for them.